| 摘要 |
PURPOSE:To decrease the hardware capacity by connecting plural number of identical arithmetic circuits each comprising a multiplier on a Galois field, an adder and m-stage of register arrays storing its adder output and selector output so as to decrease number of the m-set of register stages and to reduce the processing time required for one arithmetic circuit. CONSTITUTION:The circuit scale of GF(2<m>) is selected as M gates, then the circuit scale of the GF(2<m>) is nearly 4M gates. Considering the constitution of one word from m-bit to 2m-bit, the processing speed by 1PE is 10-20Mwps(word/sec), then the speed is increased from m(10-20)Mbps into 2m(10-20)Mbps, then doubled. In selecting the substantial processing speed as bps,number of the required processing elements PE is (t), because k=(2t/m) and m=2. Thus, in increasing the constitution of the Galois field from GF(2M) into GF(2<2>M), the increase in the circuit scale in the same processing speed is doubled. The circuit scale is decreased by having only to increase number of register stages of the PE used in RS coder/decoder.
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