发明名称 INTEGRATED MEMORY
摘要 PURPOSE:To magnify the capacity of a memory and to decrease the fault action of a sense amplifier by connecting only a set of selected digit lines with the sense amplifier and passing the two digit lines on respective memory cells. CONSTITUTION:The sense amplifier 37 is connected with a set of the digit lines 23 and 24 and the other set of the digit lines 25 and 26 through gate transistors T21, T22, T23 and T24 and input joints N21 and N22. Reference electric potential generation circuits 35 and 36 are respectively connected with the joints N21 and N22, and simultaneously the memory cells 31, 32, 33 and 34 as many as the lines are connected with the lines 23, 24, 25 and 26. The fault action of the amplifier 37 can be decreased by connecting only a set of the selected digit lines with the amplifier 37, decreasing the parasitic capacity of the digit lines and reducing the division ratio to the storage capacity of the memory cell. The density of the memory is raised by minimizing the pitch of the two digit lines passing on the memory cells and simultaneously the capacity of the memory can be magnified by minimizing the area of the memory cells.
申请公布号 JPS63164094(A) 申请公布日期 1988.07.07
申请号 JP19870082426 申请日期 1987.04.03
申请人 NEC CORP 发明人 TAKADA TADAHIDE
分类号 G11C11/401;G11C11/34 主分类号 G11C11/401
代理机构 代理人
主权项
地址