| 摘要 |
PURPOSE:To reduce a pattern area by constituting the titled circuit by 1st-4th transfer gates and 1st-4th clocked buffers so as to eliminate the delay time for a data. CONSTITUTION:1st and 2nd clocked buffers 22-1, 22-2 transfers a data in the right direction and the 3rd and 4th clocked buffers 22-3,224 transfer the data in the left direction. The 1st and 2nd transfer gates 21-1, 21-2 fetch and output the data at the data transfer in the right direction and the 3rd and 4th transfer gates 21-3, 21-4 hold the data in this case. The 3rd and 4th transfer gates 21-3, 21-4 fetch and output the data in the data transfer in the left direction and the 1st and 2nd transfer gates 21-1, 21-2 hold the data in this case. The transfer direction of the data is switched by a control signal R/U to attain the data transfer in two ways. Thus, the delay time in each delay type flip-flop circuit D-FF is eliminated and the extended wiring is avoided. |
