| 摘要 |
PURPOSE:To decrease the circuit scale and to attain high speed processing by varying the amount of delay of delay circuits connected in cascade corresponding to the replacement pattern of a time slot location so as to replace time slots. CONSTITUTION:The switch array consists of delay circuits of 2(log2N-l) stages and switch circuits of in total (2log2N-1) stages by using a 2X3 switch 303 at the input terminal, a 3X2 switch 311 at the output terminal and plural 3X3 switches 304-310 connected in cascade via delay circuits 312-317 inbetween. In deciding control signals 325, 327 and 329 corresponding to the replacement pattern of the time slot position in an input TDM frame, a link of a delay circuit with a proper delay amount is selected and the time slot is replaced.
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