| 摘要 |
PURPOSE:To speed up a processing by subjecting an analog signal to sample-and- hold and A/D-converting the high-order bit signal, thereafter, D/A-converting it, subtracting it from an initial sample-and-hold value, and dividing complementarily each part of a sample-and-hold circuit into two. CONSTITUTION:An analog signal A1 is divided into two by a switch S1 and held by sample-and-hold S/H circuits 21, 22. Output signals A21, A22 of the S/H circuits 21, 22 are A/D-converted 3 to digital signals D11, D12 of the high-order (n-m) bits through a changeover switch S2, and also, inputted complementarily to a subtracter 5 through a switch S3. Digital signals D11, D12 are latched 71, 72 complementarily, and its outputs are D/A-converted 4 and subtracted 5 from the signals A21, A22. Subtracted outputs A41, A42 are brought to S/H 81, 82 complementarily, A/D-converted 6, and digital signals D21, D22 of the low-order (m) bits are outputted. On the other hand, the digital signals D11, D12 of the latching circuits 71, 72 are outputted as the signals of the high-order (n-m) bits, the outputs of the A/D converting circuit 3 and 6 are synthesized, and the output of (n) bits is obtained. In such a way, the processing is executed at high speed.
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