| 摘要 |
PURPOSE:To simplify the constitution of a decoder by utilizing a shift register recovering run-length and a shift register detecting an address code so as to detect the address code and to recover the run-length at the same time. CONSTITUTION:A code data 50 is inputted to a sift register 56 via a code data control circuit 53 from the MSB (most significant bit) synchronously with a clock 51. A timing control circuit 52 gives a shift clock 67 to the shift register 56, a shift-in clock and a shift-out clock 61 to an FIFO 54 and supplies a count clock 64 to a run-length counter section 59. Moreover, when an address code is detected from the address code detection section, the shift clock 67, the shift-in clock 60 and the shift-out clock 61 are all masked. Thus, the address code is detected and the run-length is recovered simultaneously.
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