| 摘要 |
PURPOSE:To perform high-speed processing without using the moving means of an optical system by varying a reference clock by using 2nd clocks whose number corresponds to a variable power rate, processing image data on a line being processed currently by data on a line in a dither pattern to be outputted next, and utilizing data on this one line. CONSTITUTION:A clock generating circuit 2 generates a write clock WCLK corresponding to the variable power rate for the reference clock CLK. A comparator 5 compares data on a line being read currently with data on a line of a dither memory 4 to be outputted next. A comparator 6, on the other hand, compares the data being read currently with data of the memory 4 to be outputted next. An address counter 3 updates and generates addresses of memories 7 and 8 where the comparison results of the comparators 5 and 6 are stored respectively in synchronization with the WCLK. Consequently, an address supplied to the memory 4 is varied according to the set variable power rate and data of the dither pattern to be outputted next is stored at the time of enlargement to compensate deficient lines with the storage contents of the memory 8, but the output of the memory 7 is thinned out as many as excessive lines at the time of reduction. Thus, enlargement and reduction in a subscanning direction are carried out and the data of the dither pattern is still unchanged at this time, so that pattern is not destroyed. |
