发明名称
摘要 PURPOSE:To detect and display a reception rate easily and accurately by generating the same signal as a transmitted prescribed pseudo-random signal at a reception side, by making a bit-to-bit comparison between the both and by counting mumber in dissidence. CONSTITUTION:Clock generating circuit 19 generates a clock pulse synchronizing with a received signal. Clock gate circuit 21 receives the clock pulse from circuit 19 and outputs a 256-bit clock pulse as a gate pulse while binary information is superposed at the 20th H. Further, gate pulse generating circuit 22 generates gate pulses in the 1st 16-bit and following 240-bit periods of the above-mentioned binary information signal. The received signal, on the other hand, is delayed and sampled by delay sampling circuit 20, whose output is supplied to comparison signal generating circuit 23. Circuit 23 generates a comparison PN code signal from outputs of circuits 20-22. Comparing circuit 24 compares signals of circuits 20 and 23 with each other, bit by bit, and when both the signals disagree, generates a dissidence detection signal. This output is counted by counting circuit 25, whose count value is displayed 26.
申请公布号 JPS6332316(B2) 申请公布日期 1988.06.29
申请号 JP19790161790 申请日期 1979.12.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HIRASHIMA MASAYOSHI
分类号 H04N7/025;H04N7/03;H04N7/035 主分类号 H04N7/025
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