| 摘要 |
In a self-diagnosable integrated circuit device comprising sequential circuit elements in an internal logic circuit, a first test pattern signal is successively produced in a test mode from a test pattern generating circuit and stored into the sequential circuit elements with a first timing signal given from a timing signal generating circuit to the internal logic circuit. After storage of the first test pattern signal into the sequential circuit elements, a second test pattern signal is produced from the test pattern generating circuit with a second timing signal given to the internal logic circuit. The internal logic circuit carries out processing operations determined for the second timing signal and produces an output data signal which is dependent on the first and the second test pattern signals and which is evaluated by an external circuit. Storage of the first test pattern signal may be made by forming a scan path through a gate circuit connected to each sequential circuit element. Alternatively, each sequential circuit element may be loaded with the first test pattern signal by assigning addresses to the respective sequential circuit elements and by indicating each address.
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