| 摘要 |
PURPOSE:To perform high-speed stansfer control efficiently by controlling address information transfer and data information transfer on a bus at non-time- division timing in memory initialization mode. CONSTITUTION:An information processor consists of a CPU 10 and a memory device 20. This CPU 10 consists of a microprocessor 11, an address conversion part 12, etc, as function block and is further provided with a two-way bus driver 145 and a timing control part 14 which generates a bus control timing signal at the time of a newly defined initialization mode instruction and a bus control timing signal the time of an operation mode instruction to control the bus driver in the CPU 10 and the bus driver in the memory device 2 with the respective timing signals. Further, the memory device 20 has memory 21'-23'. Consequently, transfer on the bus is controlled at non-time-division timing in memory initialization mode by using respective specific parts to eliminate a waste of bus bits.
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