发明名称 APPARATUS AND METHOD FOR CONTROLLING POWER FEEDER
摘要 A clock control system for a multiple channel electric power system includes a master clock circuit (28) and control circuitry (40) in each parallel connected channel. The channel control circuits are initially phase-locked to a master clock signal. If the master clock signal is out of a preselected frequency range, the individual channel control circuits (38, 40) are decoupled from the master clock signal and one of those circuits produces a backup clock signal. The control circuits in the remaining channels are then phase-locked with the backup clock signal to provide continued parallel system operation.
申请公布号 JPS63154027(A) 申请公布日期 1988.06.27
申请号 JP19870306818 申请日期 1987.12.03
申请人 WESTINGHOUSE ELECTRIC CORP <WE> 发明人 DONARU YUUJIN BEIKAA;MAAZA AKUMARU BETSUGU
分类号 G05F1/00;G04G7/00;H02J3/38;H03L7/00 主分类号 G05F1/00
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