| 摘要 |
PURPOSE:To enable operation at high speed by forming a negative-polarity impurity layer only in the vicinity of a high concentration layer without forming it under a channel layer. CONSTITUTION:An N type impurity layer 5 is formed to a semi-insulating GaAs substrate 4, and a gate electrode 1 is formed on the surface of the layer 5. N<+> high concentration layer 6, 7 are formed on both sides of the electrode 1. Negative-polarity P type layers 9, 10 are formed under the layers 6, 7, and ohmic electrodes 2, 3 for a source and a drain are formed on the layers 6, 7. According to such constitution, mutual conductance is approximately the same as before, but drain conductance is reduced, and variation by gate length is minimized regarding gate breaking voltage. Consequently, a short channel effect can be reduced, and logic operation at high speed can be obtained. |
