| 摘要 |
PURPOSE:To maintain the relation of phase of the clock in a prescribed relation by deciding the semiconductor junction comprising plural inverters and a delay in a logic operation circuit while taking a delay in a multiplexer into account. CONSTITUTION:Since flip-flop circuits 3, 39 have the same constitution, the delay time caused by the flip-flop circuits and the effect of fluctuation of power voltage are identical actually. A sum of delay tau2+tau3 of a delay tau2 by the semiconductor junction 37 corresponding to the delay of the flip-flop circuit 38 outputting a selection clock C2 selecting a high-order digit and a delay tau3 caused by a multiplexer 1 is made equal to the sum of a delay tau4' by the semiconductor junction 4 and a delay tau5 of the logic operation circuit 5. Thus, the relation of phase of selection clocks C1, C2 of the multiplexer 1 and a read clock Cr of the latch circuit 2 is kept to a required relation.
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