PERFORMANCE MEMORY BUS ARCHITECTURE

摘要

An improved performance memory bus architecture comprising a standard unified bus, microprocessor system, and separate memory bus. Access to memory banks coupled to the memory bus may be made by subsystems communicating over the unified bus using the standard protocol of the unified bus, or may be made by the microprocessor using an improved access protocol method wherein an accessed memory bank generates an acknowledgement signal upon receipt of a READ or WRITE command rather than after the completion of the respective READ or WRITE operation. A further improvement comprises an Early READ/WRITE circuit that rapidly detects the initiation of a READ or WRITE command by the microprocessor by decoding standard microprocessor status signals in order to generally commence a READ or WRITE operation prior to the time that a normal READ or WRITE operation would be commenced under the prior art.