| 摘要 |
PURPOSE:To obtain an economical bit synchronization system by providing a delay part adjustable with an external signal, a part to produce a delayed information with a constant clock, information memories at every, combination of input and output lines, and a line switch part. CONSTITUTION:An output information to the switch part 2 varies its phase at every combination of an in-line 8 and an out-line 9 because of the uneveness of line lengths and elements in the switch part 2. In the delay part 3, a switched output 10 is delayed 101 with a phase difference of 1ns, the delayed information 101 is selected 102 by means of an output 12 from an internal control part to vary the delay amount at every combination of the lines for connection, and thus phases are made identical, and outputted 11. The output 11 is reproduced 9 by selecting 202 the output of an FF 201 at a time when a clock 16 is led. And the combination of the lines 8, 9 is stored in a memory 7. The internal control part 5 connects the switch 2 based on a signal from a main control part 6, and transmits the delayed information 12 based on an information in the memory 7 to the delay part 3. As a result, a delay amount calculation is not necessary at every connection, and accordingly the quantity hardwares is remarkably reduced.
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