| 摘要 |
PURPOSE:To vary a test speed optionally and to set the optimum test speed for each pattern by varying a test clock and decision timing according to information from a pattern memory. CONSTITUTION:A test clock generating circuit 3 operates according to the contents of a test program stored in a program memory 1 and the contents of the pattern memory 2 and this test clock is supplied to a sample 7 to be tested. The output signal of the sample 7 is sent to a comparing circuit 6 and compared with an expected value, but the timing of the comparison is determined by a decision timing control circuit 5 at this time. Further, a clock control circuit 4 is operated according to information on a specific location of the pattern memory 2 to vary the phase of the test clock and the phase of the decision timing signal.
|
