发明名称 |
METHOD FOR VERIFYING MASK PATTERN |
摘要 |
PURPOSE:To make it possible to verify a mask pattern also when an inverter even-number stage serial connection circuit is inserted by grouping inverters connected in series and assigning indexes to nodes connected to the inverters in the group. CONSTITUTION:A circuit diagram is formed and a CMOS mask pattern e.g. is designed based on the circuit diagram. A signal name and character data serving as initial corresponding indexes to the signal name of the circuit diagram are applied to a mask pattern diagram and then digitized to obtain mask pattern data. Then the information of elements and connecting relation of respective elements is extracted from the mask pattern data by executing graphic arithmetic operation or the like by means of the mask patterns. Then, the inverters are extracted and grouped and indexes are applied to the nodes connected to the inverters in the groups. At the time of comparing the formed circuit diagram with the original circuit diagram, the comparison is executed up to the node having the final index to verify the connection of the circuit. |
申请公布号 |
JPS63137372(A) |
申请公布日期 |
1988.06.09 |
申请号 |
JP19860283148 |
申请日期 |
1986.11.29 |
申请人 |
DAINIPPON PRINTING CO LTD |
发明人 |
JINBO YASUO;KASHIMOTO YOSHIHIRO;WATANABE TOSHIO;ISHIDA KOJI |
分类号 |
G03F1/00;G03F1/84;G06F17/50;H01L21/027;H01L21/30;H01L21/66 |
主分类号 |
G03F1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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