| 摘要 |
PURPOSE:To improve the response of a PLL circuit and to reduce the locking time by supplying an output of a synthesis means to a voltage controlled oscillator via a low pass filter. CONSTITUTION:A phase error of an input data S3 is detected by phase error detection means 11, 2 based on a clock signal S1 from a voltage controlled oscillator 15. Every time the phase error S6 is detected. a prescribed width of reference signal S1 is generated by reference signal generating means 13, 14. Moreover, the clock signal S1 is subject to 1/2 frequency division by a frequency division means 16 to obtain a recovered clock S2 and the recovered clock S2 is phase-shifted by a phase shift means 18 based on the clock signal S1. The phase-shifted recovered clock S8 and ths reference signal S7 are ANDed by an AND circuit 19 and the AND output S9 and the detected phase error S6 are synthesized by a synthesis means 20. The synthesized output S10 is fed to the oscillator 15 via a low pass filter 21. |
