发明名称 CACHE MEMORY CONTROL SYSTEM
摘要 PURPOSE:To prevent processing performance from being lowered due to the increase of the registration of a resident file, by stocking the address of a linking means at the forefront of the resident file linked at every memory unit number by a resident file registering/linking means in a linking forefront address stocking means. CONSTITUTION:Responding to a request to use a cache memory from a processor 4, the address of the linking means at the forefront of a memory unit to be used is read out from the linking forefront address stocking means by using the memory unit number of a request file. And a resident file registering address is read out from the resident file registering/linking means 6 by the above address. Afterwards, the memory unit number is read out from a resident file registering means 5 by the address, and the memory unit number is compared with a requested memory unit number, thereby, the residence/non-residence of the request file is decided. In such way, it is possible to obtain a cache memory control system in which the processing performance is prevented from being lowered even when the number of registration of the resident file is increased.
申请公布号 JPS63129442(A) 申请公布日期 1988.06.01
申请号 JP19860276208 申请日期 1986.11.19
申请人 NEC CORP 发明人 ICHIKAWA FUMIO
分类号 G06F12/08;G06F12/12 主分类号 G06F12/08
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