发明名称 SAMPLE/HOLD CIRCUIT
摘要 PURPOSE:To obtain a linear sampling voltage without a phase lag by connecting two transistors (TRs) respectively between a differential amplifier and a power source, and controlling a shunt by the TR so that a current Miller circuit goes to an ON-state even during its holding period, in a sample/hold circuit made into an IC. CONSTITUTION:In a sampling period, the NPN type TR Q4 of a switching circuit 3 and the NPN type TRs Q1 and Q2, which made a couple in the differential amplifier 1, are turned ON, and the NPN type Q5 and Q6 to make a couple are turned OFF, and the instantaneous value (i) of the output of the current miller circuit 2 corresponding to a signal to be sampled S.S.i is sent into a holding capacitor C from the Q3. Next, in the holding period, the Q4 of the circuit 3 and the Q1 and the Q2 of the amplifier 1 are turned OFF, and the Q5 and the Q6 are turned ON, and the pair of output currents I, I of the circuit 2 is absorbed into a current source J by the Q5 and the Q4d6, but never absorbed into the capacitor C. Accordingly, for the TR Q3 of the circuit 2, it is not necessitated to make it repeat ON-OFF during the sampling period.
申请公布号 JPS63127498(A) 申请公布日期 1988.05.31
申请号 JP19860271889 申请日期 1986.11.17
申请人 SONY CORP 发明人 NIIMURA TSUTOMU;KURODA OSAMU;KAWAI RIYUUICHIROU
分类号 H03K7/02;G11C27/02;H03K17/60 主分类号 H03K7/02
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