System for determining occurrence sequence of sampled data

摘要

In a logic analyzer including first and second sampling channels operative with different clocks independently, a system for determining sequence in time in which the sampled data are generated in both sampling channels includes a memory interposed between the first and second sampling channels. The memory has a data input supplied with the address data of the first sampling channel, an address input supplied with the address data of the second sampling channel and a data write input supplied with the clock signal of the second sampling channel.