摘要 |
The invention pertains to programmable fast logic. The logic gate of the invention comprises two parallel-mounted inverters comprising one transistor and one saturable load. The second inverter is powered through a transistor, the electrode gate of which, linked to the drain, is joined to the drain of the first inverter which may have additional inputs (OR function). A triplet of three series-mounted logic gates comprises a programming input at the third gate, a re-looping output and, in the case of a sequence of triplets, re-looping inputs at the first gate of the first triplet. A programmable logic circuit is obtained by a sequence of series-mounted triplets which are all looped back to the first gate of the sequence. The programming is obtained by placing one or two programming inputs at the logic 0 level. Application: Programmable frequency divider circuits in which the ratios follow one another, one by one.
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