发明名称 TESTING SYSTEM FOR DMA TRANSMISSION CONTROL CIRCUIT
摘要 PURPOSE:To omit a large-capacity memory and a large quantity of test data and to decrease the test facilities together with reduction of the test cost, by checking whether the number of words of the received transfer data is equal to the prescribed number of words or not and at the same time having a cyclic redundancy check of the transfer data. CONSTITUTION:When the transfer data transmitted from a DMA transmission control circuit 1 is received by a DMA reception control circuit 2, the received data is not stored and the number of transferred words of the data is written into a transfer word number counter 3. Then it is checked whether the number of said transferred words is equal to the prescribed number of words or not. At the same time, the CRC (cyclic redundancy check) arithmetic of the data is carried out by a CRC arithmetic circuit 4. This arithmetic result is written to a CRC arithmetic result register 5 for check of normalcy of the circuit 1. Thus it is possible to omit a large-capacity memory which stores the transfer data and also to finish the CRC in a short time together with omission of a large quantity of test data. As a result, the reduction of cost is attained with the test facilities and test itself.
申请公布号 JPS63124158(A) 申请公布日期 1988.05.27
申请号 JP19860271331 申请日期 1986.11.13
申请人 NEC CORP 发明人 HICHIHARA MASAAKI
分类号 G06F13/28;G06F13/00;H04L1/24;H04L13/00;H04L29/14 主分类号 G06F13/28
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