| 摘要 |
PURPOSE:To obtain a device with resulting no malfunction, by writing a data represnting a processing state on a non-volatile memory when the drop of a power source voltage is detected. CONSTITUTION:The output lowering detection circuit 551 of a power source monitoring circuit 55 sets a power source lowering detection signal at an L level at a prescribed time immediately after the applying of a power source, and at a time when the constant voltage VCC of +5V that is the output of constant voltage power source circuit goes down less than +4.5V. Based on the above state, an MPU50 saves the content of a CPU register at need by performing an interruption processing. And after the lapse of a prescribed short time, the above stated power source output lowering detection signal (L level) delayed by a delay circuit 552 is outputted as a reset signal. Thereby, the MPU50, an S1CPU62, an S2CPU63, an S3CPU, and an I/O device 56 are initialized, and the chip select of a RAM531 and a real time clock 532 are disabled via a battery backup circuit 533, then, read and write are prohibited. |
