| 摘要 |
PURPOSE:To reduce the number of wiring tracks in wiring regions by a method wherein, when a plurality of cell rows are arranged in partial circuits which are obtained by dividing an LSI chip functionally, the cells which are to be connected to external terminals are arranged in the circumferential rows preferentially. CONSTITUTION:When a plurality of cell rows 5 and wiring regions 6 between the cell rows are arranged, at first the cells which are to be connected to external terminals are arranged in the circumferential rows. For instance, the cells A, B, C, D, E and F are arranged in the circumferential cell row. After those cells are arranged, the cells which are not connected to the external terminals are arranged. With this constitution, the increase of the number of wirings in the center parts of the wiring regions caused by the wirings for the external terminals is avoided so that the number of wiring tracks in the wiring layers can be reduced. |
