| 摘要 |
PURPOSE:To raise a threshold voltage of a P-channel parasitic MOS transistor without an N well by about 1-6 [V] and to reduce a leakage current in such a way that phosphorus ions are implanted by making use of a silicon nitride film as a mask with a view to forming a LOCOS structure. CONSTITUTION:After resist layers 12, 13 have been removed, phosphorus ions 16 are implanted by making use of a silicon nitride film 10 as a mask. After this assembly has been thermally oxidized by making use of the silicon nitride film 10 as a mask, a thick field oxide film (LOCOS structure) 17 is formed. After the silicon nitride film 10 has been removed, a polysilicon layer 18 is grown by a CVD method; after patterning, a gate electrode is formed. After a thin oxide film 19 has been formed by thermal oxidation, a source region and a drain region of a P channel aud an N channel are formed by ion implantation. After an interlayer insulating film 20 has been formed and a contact opening has been made, aluminum 21 is sputtered. After patterning, an N-channel MOS transistor, a P-channel MOS transistor and a P-channel parasitic MOS transistor are completed. |
