| 摘要 |
PURPOSE:To prevent the level of GND from floating when an output buffer is changed simultaneously by providing a delay circuit at a supplying path to respective output buffers of a clock signal which is the synchronizing signal of the output buffer. CONSTITUTION:A clock signal, which is the synchronizing signal of an output buffer, is changed at output buffers OUT1 and OUT2 since the OUT2 is delayed for the part to add a delay circuit 6b. At an OUT1 and an OUTn, only (n-1)X(delay per one step) is delayed and the signal is outputted. Thus, by dislocating that respective outputs are changed, the time when a through current flows is dislocated, and whereby, it can be suppressed that the large current simultaneously flows and the level of the GND floats.
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