| 摘要 |
PURPOSE:To eliminate an equalizing pulse and noise not in the synchronous with the horizontal synchronizing pulse by gating a horizontal synchronizing separation output by a pulse synchronously with a horizontal synchronizing pulse when a horizontal oscillator is synchronized (locked) with an input video signal. CONSTITUTION:A horizontal synchronizing separator circuit separates a horizontal synchronizing pulse whose period is H from a video signal and when the horizontal synchronizing pulse and a horizontal oscillator AFC are synchronized and the output of the horizontal lock discrimination circuit is 1, a NAND gate 1 outputs a pulse being the inversion of the horizontal synchronizing pulse (synchronously with the horizontal synchronizing pulse). Thus, the output of the horizontal synchronizing separation circuit is gated by the pulse synchronously with the horizontal synchronizing pulse and the result is led to an AFC loop. That is, in the lock state, the pulse of 1/2H period such as an equalizing pulse is blocked for passing by the gate 2.
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