发明名称 BIT ERROR DISTRIBUTION MEASURING APPARATUS
摘要 PURPOSE:To enable quantitative determination of distribution characteristic of the number of bit errors in a block, by measuring the number of errors per block for blocks with a fixed sample to perform a statistic processing. CONSTITUTION:A frame counter 102 counts clocks 101 to output frame pulses 103 per block as preset and a delay circuit 104 outputs a clear pulse 105 delayed by one time slot from the frame pulses. On the other hand, an error counter 202 counts and outputs error pulses 201, for example, by the clocks and a block counter 204 adds up errors in one frame to output the number of errors within one block. Then, a CPU300 reads out an output of the block counter 204 and performs a statistic processing of the results thereby enabling the measuring of bit errors with a block as a unit, as set according to the block length in the error correction.
申请公布号 JPS63113367(A) 申请公布日期 1988.05.18
申请号 JP19860258312 申请日期 1986.10.31
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 AIKAWA SATOSHI;SAITO YOICHI
分类号 G01R31/00;H04L1/00;H04L1/20 主分类号 G01R31/00
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