| 摘要 |
PURPOSE:To eliminate a fault at output inversion by setting a prescribed relation to a delay amount of a couple of delay circuits of a CMOS inverter receiving a signal input directly and with a delay and connecting the output to a common buffer. CONSTITUTION:A P-channel transistor (TR) P1 and an N-channel TR N1 of the 1st CMOS inverter IV1 are connected in series between a power supply VDD and a ground VSS, a signal from an input signal node 10 is inputted to its gate and the output is given at an output node 13. Similarly, the 2nd CMOS inverter IV2 consists of a P-channel TR P2 and an N-channel TR N2, its output is connected to the output node 13 and delay circuit 11, 12 are connected to each pre-stage. The delay circuits 11, 12 consist respectively of N-channel TRs N3, N4 whose gate receives a potential VDD and P-channel TRs P3, P4 whose gate receives a potential VSS, and the size of the TR P3 is selected larger than that of the TR P4 and the size of the TR N4 is selected larger than that of the TR N3. Thus, overshoot/undershoot at output inversion and the through- current are suppressed. |
