发明名称 PLL CIRCUIT
摘要 PURPOSE:To attain fast lockup and stable ripple elimination by supplying a control voltage to a voltage controlled oscillator circuit or a filter circuit in revising a frequency divider ratio of a programmable frequency divider. CONSTITUTION:An oscillated output of a VCO 4 is frequency-divided by the programmable frequency divided 5 and the phase of its frequency division output and the phase of an oscillated output from a reference oscillation circuit 1 are compared by a phase comparator circuit 2. An output of the phase comparator circuit 2 is given to the VCO 4 via a filter circuit 3. In revising the frequency division ratio of the programmable frequency divide 5, a control voltage from a control voltage supply circuit 7 is fed to the filter circuit 3 by a control circuit 6 to set the oscillation output of the VCO 4 in the vicinity of a desired frequency.
申请公布号 JPS63111726(A) 申请公布日期 1988.05.17
申请号 JP19860257805 申请日期 1986.10.29
申请人 SANYO ELECTRIC CO LTD 发明人 SANO MASAYUKI
分类号 H03L7/187;H03L7/18 主分类号 H03L7/187
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