| 摘要 |
PURPOSE:To ignore a clock skew thereby to facilitate a timing design by providing one clock driver in a peripheral region, and wiring the output terminal of the driver with clock wirings. CONSTITUTION:A clock driver 4 is provided in a peripheral region 6, clock wirings 3 drawn in parallel with all transistor rows 1 are prepared for wiring regions 2, and the output terminal of the driver 4 is wired by wirings 5 to the wirings 3. Accordingly, since the simultaneous timing of the clocks in all the circuits is proved by the drivers 4, the wirings 5, and the clock wirings 3, a clock skew can be ignored. |
