| 摘要 |
PURPOSE:To reduce a wiring resistance and moreover to flatten an interlayer insulating film by a method wherein, when multilayer interconnections are provided on a semiconductor substrate, these are used being added metals of a resistance lower than that of Al, the wirings are laminated through CVD insulating films and furthermore, the relation between the interwiring interval and the thickness of wiring films, that is, the value of the interval to the film thickness is controlled to 1 or less. CONSTITUTION:A thick field oxide film 2 is provided on a P<->-type Si substrate 1 using a P-type channel stopper region 3 as an underlay and N<+>-type source and drain regions 6 are formed by diffusion in the surface layer part of the substrate 1 being surrounded with this film 2. Then, a thin gate SiO2 film 4 is adhered on these regions, a gate electrode 5 is provided thereon and the whole surface is covered with an interlayer PSG insulating film 7 formed by a CVD method. After that, connection holes are opened on the film 7 and lower wirings to be connected to the regions 6 and lower wirings 9 to position on the film are formed. At this time, the wirings 9 are constituted of Al surrounded with copper and silver, an interlayer insulating film 10 formed by a CVD method is adhered thereon and an upper wiring 11 is provided thereon. At this time, the thickness of the wirings 9 and the interval between the wirings 9 and 11 are specified.
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