| 摘要 |
<p>PURPOSE:To omit the external circuits and to increase the data access speed by using plural input pins for data complete signals and producing an OR within a microprocessor. CONSTITUTION:The inverse of DC0 input signal is supplied to test machine 21 via an inverter 28, a NOR gate 29 and an inverter 30, while the inverse of DC1 input signal is supplied to the machine 21 via an inverter 32, the gate 29 and the inverter 30 respectively. For the input signal of a microprocessor, plural inverters are generally cascaded at the stages following an input pad. These inverters are replaced with NOR and an OR is secured. The circuit delay due to the cascade of inverters and the circuit delay caused when the circuit delay serves as a NOR by an amount equal to a stage are very small in a CMOS process. Thus it is not required to produce an OR through an external circuit, therefore, the data access speed is increased.</p> |
