发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To obtain a preferable VCE characteristics by providing upper and lower separating regions intruded into a semiconductor substrate to divide the substrate into two insular regions, and providing a high concentration buried layer on the substrate when one is used as a vertical PNP transistor region and a buried layer on a first epitaxial layer when the other is used as an NPN transistor region. CONSTITUTION:P<+> type upper and lower separating regions 25 intruded into a P-type Si substrate 21 are provided in the substrate 21 to divide the substrate 21 into two insular regions 26, 27, the region 26 is used as a vertical PNP transistor region, and the region 27 is used as an NPN transistor region. Then, N-type first epitaxial layer 22 and an N-type second epitaxial layer 23 are laminated and grown on these regions, an N-type base region 30 surrounded by a P<+> type collector leading region 29 is formed on the vertical PNP region, an emitter 31, a collector 32 are formed thereon. At this time, an N<+> type first buried layer 24 is provided on the substrate 21. A base 33 and an emitter 34 are formed on the NPN region, and an N<+> type buried layer 38 therefor is provided on the layer 22.
申请公布号 JPS6377144(A) 申请公布日期 1988.04.07
申请号 JP19860222626 申请日期 1986.09.19
申请人 SANYO ELECTRIC CO LTD 发明人 TABATA TERUO;NISHII MASAHARU;KANEKO KAZUO
分类号 H01L21/8228;H01L27/082 主分类号 H01L21/8228
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