发明名称 FAST COMPLEMENT FORMING CIRCUIT
摘要 PURPOSE:To attain the fast complement forming for a lengthy bit data, by providing a complement forming means by a specific logic, which finds two complements for a binary number of multidigit, and inputs a carry 1 to the least significant order. CONSTITUTION:The titled circuit is to find the two complements for the binary number of multidigit, and it is provided with a means in which the carry 1 is inputted to the least significant order, and which obtains a complement forming result x' by the following logic assuming a carry from a low-order as Cn, an original number on which complement forming is applied as (x), and the carry to a high-order as Cn+1. By introducing the carry 1 to the least significant bit, (x=x') can be obtained from table. Since the carry Cn+1 is 1 if the least significant digit x1 is 0, the next digit x2 also goes to (x2=x2'), and since the Cn+1 is 0 if the x1 is 1, -x2 is equal to x2', and a logic is executed in such way, then, two complements for the binary number can be obtained. In such a way, it is possible to obtain a fast complement forming circuit for multidigit data.
申请公布号 JPS6375930(A) 申请公布日期 1988.04.06
申请号 JP19860221017 申请日期 1986.09.19
申请人 FUJITSU LTD 发明人 UTSUNOMIYA SHINICHI;YAMADA KATSUHIKO;ISANE KENJI
分类号 G06F7/38;G06F7/50;G06F7/506;G06F7/508 主分类号 G06F7/38
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