发明名称 |
Design support apparatus for semiconductor devices |
摘要 |
A design support apparatus for semiconductor devices that is used to quickly arrange a non-logic cell for reducing electromagnetic radiation from a semiconductor device at the time of designing it. In this design support apparatus for semiconductor devices, a layout section does a layout for logic cells and wiring patterns to connect the logic cells. An arranged site detecting section detects an arranged site, being a site which contains neither the logic cells nor a prohibited area, after a layout is done by the layout section. A non-logic cell pattern store section stores non-logic cell patterns. A prohibited area containing site detecting section detects a prohibited area containing site, being a site which only contains a prohibited area. A non-logic cell arranging section arranges non-logic cells on the arranged site. Furthermore, the non-logic cell arranging section compares the arrangement of the prohibited area on the prohibited area containing site with a non-logic cell pattern and arranges non-logic cells only on a site where these do not conflict with each other.
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申请公布号 |
US2001039643(A1) |
申请公布日期 |
2001.11.08 |
申请号 |
US20010808344 |
申请日期 |
2001.03.15 |
申请人 |
KURODA SACHI;SUGIOKA TOSHIAKI;OSAJIMA TORU;ICHINOSE SHIGENORI |
发明人 |
KURODA SACHI;SUGIOKA TOSHIAKI;OSAJIMA TORU;ICHINOSE SHIGENORI |
分类号 |
G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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