Combined circuit switch and packet switching system
摘要
Apparatus for and a method of inserting circuit switch information and packetized data into different time slots of a time division multiplexed bus. A memory having a location individual to each time slot is written with information specifying whether the time slot individual to each location is to serve circuit switch information or packet data. The readout of each memory location during the occurrence of it's associated time slot controllably effects the application of either the circuit switch information or the packet data to the bus. Packet data can be inserted into each time slot not currently being used by the circuit switch. A special information bit is inserted into each time slot to specify whether the remainder of the bits of the time slot represents circuit switch or packet information. The information bit is used by receiving apparatus to steer the bits of each time slot to either a receiving circuit switch or a receiving packet switch.
申请公布号
US4731785(A)
申请公布日期
1988.03.15
申请号
US19860876613
申请日期
1986.06.20
申请人
AMERICAN TELEPHONE AND TELEGRAPH COMPANY;AT&T INFORMATION SYSTEMS INC.
发明人
FERENC, JAMES J.;GEBHARDT, ROBERT W.;GRIMES, GARY J.;MORGAN, JR., EDWARD B.;SELLERS, III, GABE A.