LOW CAPACITANCE TRANSISTOR CELL ELEMENT AND TRANSISTOR ARRAY

摘要

A transistor cell element that may be used alone or in a matrix array in large scale integrated circuits includes a substrate onto which an isolation region is fabricated. Inner and outer charge carrier regions having a high density of first charge carriers is formed in the substrate to define a channel region therebetween. The inner carrier region is adjacent the isolation region so that the channel region extends in a closed loop from said isolation region, around the inner carrier region and back to the isolation region, with the outer carrier region surrounding the isolation and channel regions. The channel region has a low density of second charge carriers, having opposite charge than the first charge carriers, and a gate structure including a conductive band and an insulating layer is formed over the channel region. In one alternate embodiment, additional isolation regions may be provided with these regions interrupting the channel region. In another alternate embodiment, the isolation region extends across the cell element and divides the inner and outer carrier regions and the channel region each into two sections. On one side of the isolation region, the inner and outer carrier regions have first charge carriers with the associated channel having second charge carriers; on the other side of the isolation region, the inner and outer carrier regions have second charge carriers with the associated channel region having first charge carriers