BUS INTERFACE DEVICE FOR A DATA PROCESSING SYSTEM

摘要

A number (e.g. sixteen) of processors are connected to a central control unit by a common bus having half that number of wires (D0-D7) reserved for a byte of data or control bits, one line for a parity bit and one for a control bit. In the bus interface each line (D0-D7) is associated with two flip-flops (40,41) having direct and inverted (44) inputs of a first clock signal (CLK1). When received bits are in NRZ code with duration equal to half the clock period, output OR gates (47) reproduce resynchronised input bits. Processors divided into two equal gps. request access during one or other phase of a second clock signal. The state of access requests is indicated by memory flip-flops (48,49) when the bus is free.