| 摘要 |
A high density, multi-chip module applicable to VHSIC technology utilizing individually hermetically sealed microelectronic chip packages operable to be pretested, breadboarded and burned in prior to final module assembly. This microelectronic module comprises a multiplicity of interconnected chips in a high density fully heat sinked configuration, resulting in high clock speed and low power dissipation. This module further facilitates a short design cycle because no dedicated hard tooling is required. A packaging density is achieved which is about two and one-half times greater than the density achieved utilizing surface mounted leaded chip carriers with leads on 20 mil centers. This is because the packages are reduced in size after testing. This density increase results in a chip-to-chip line capacitance approximately half of conventional packaging due to the fact that the path lengths across the ceramic packages and across the P.C. board are reduced.
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