| 摘要 |
PURPOSE:To prevent the occurrence of noise caused at the adjustment of the delay time of a delayed output signal by selecting the operating timing of an update signal updating the content of an information signal to the end of discharge of a delay signal line. CONSTITUTION:An operating timing control circuit consists of inverters A6, A11, clocked inverters B9, B10 and a NAND circuit E, a delay output signal O1 is given to the inverter A5, an update signal L is inputted to the clocked inverter B9 respectively and the output of the NAND circuit E is given to clocked inverters B5-B8 via clocked inverters B1-B4 and an inverter A10. An output of the inverters A5, A11 is inputted to two terminals of the NAND circuit E and the output of the inverter A11 is transferred as the update signal L of the circuit block U2 of the next stage. Thus, the occurrence of noise to the delay output signal is prevented at the adjustment. |
