| 摘要 |
PURPOSE:To miniaturize a memory cell by eliminating the masking margin from gate electrodes of a selective MISFET by a method wherein electrodes of capacitance element are formed inside a capacity element forming groove. CONSTITUTION:A groove 4 is made in a semiconductor substrate 1 while the inner wall 4 is covered with an insulating film 5 composed of silicon oxide. Two electrodes 6, 8 consisting of polycrystalline silicon film are provided inside the insulating film 5 while a dielectric film 7 consisting of a silicon oxide film is provided between the electrodes 6 and 8. A capacitance element thus composed need not any masking margin from a gate electrodes 12 of selective MISFET since a capacitance element is provided inside the groove 4 only but not on the substrate 1. In such a constitution, one electrode 8 is connected to the substrate 1 through the intermediary of a p<+> type semiconductor region g while the other electrode 6 is connected to a drain region 14 of selective MISFET through the intermediary of an n<+> type semiconductor region 10. |
