发明名称 |
Video data processing circuit employing plural parallel-to-serial converters and look-up tables |
摘要 |
A video data processing circuit eanbles an image to be displayed at a higher resolution on an image display unit such as a CRT display unit without the need for high speed parallel-to-serial (P/S) conversion and high speed accessing to look-up tables. Video data each composed of k bits are read in parallel from first to ith video RAMs (VRAMs) and supplied to a corresponding one of first to jth P/S converters. Each of the first to jth P/S converters parallelly stores those k bit video data. Each of the P/S converters serially outputs the stored video data one by one at a first time interval. The video data from the first P/S converters are supplied to a first look-up table, and similarly the video data from the second P/S converters to jth converters are supplied respectively to second to jth look-up tables. Each of the first to jth look-up tables convert the supplied video data into color data. The color data outputted respectively from the first to jth look-up tables are supplied to a selector which outputs the supplied color data one by one at a second time interval of one jth of the first time interval.
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申请公布号 |
US4727423(A) |
申请公布日期 |
1988.02.23 |
申请号 |
US19860885926 |
申请日期 |
1986.07.15 |
申请人 |
NIPPON GAKKI SEIZO KABUSHIKI KAISHA |
发明人 |
KANEKO, KOHICHI;SUZUKI, SATIO;KAWAKITA, YASUHITO |
分类号 |
G09G5/36;G09G5/06;(IPC1-7):H04N5/14;H04N9/64 |
主分类号 |
G09G5/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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