| 摘要 |
PURPOSE:To reduce an area of a transfer memory cell, by making transfer KOS transistors in a semiconductor memory such as a static RAM memory cell be formed inside the second-layered polysilicon layer. CONSTITUTION:Source regions in transfer MOS transistors Q3 and Q4 are respectively connected with data lines D18 and -D16 through ohmic contact parts 10 and 11. Source and drain regions of the transfer MOS transistors Q3 and Q4 are united with load resistors P1 and R2, respectively, inside the branch layer of the second layered polysilicon layer 5. Since the static RAM memory cell is thus formed by laminating the transfer MOS transistors in three- dimensional structure, the area of this cell is remarkably reduced. Because the area of drain regions 1a and 2a serving as nodes N1 and N2 of driver MOS transistors Q1 and Q2, respectively, is larger than that of the cell of the same area and of a conventional structure, this memory becomes large in node capacity and strong against disturbance caused by alpha rays or the like. |
