| 摘要 |
PURPOSE:To obtain an integrated circuit device which facilitates a scan test including a circuit block which has an asynchronous order circuit integrally by providing a scan register and a latch circuit connected to the scan register between circuit blocks to be tested and their connection part. CONSTITUTION:Scan registers 8-16 and latch circuits 17-25 connected to the scan registers 8-16 are provided among circuit blocks 71-73 consisting of combinational circuits for order circuits and at their connection parts. Then a through-state is established in normal operation from input terminals in the scan register 8-16 to the output terminal of the 1st latch and in a latch circuit connected to the output terminal of a 1st latch, so that input and output terminals of corresponding circuit blocks 71-73 are connected. In test operation, on the other hand, latch circuits connected to the output terminals of the 1st latches of the scan registers 8-16 are placed in a nonthrough-state to hold test data which is applied last even in scan mode, so that the data is applied to the corresponding blocks 71-73 continuously. |
