摘要 |
PURPOSE:To secure sufficient protective operations and shorten a propagation delay time to obtain a high speed, by connecting respective gates of a P channel field effect transistor (FET) and an N channel FET individually with definite diffusion resistances. CONSTITUTION:An input terminal 12 is connected with a gate of FET (Qp) through an N<+> diffusion resistance RN, and with a gate of FET(QN) through a P<+> diffusion resistance RP. Consequently, the value of resistance obtained by viewing the C-MOS inverter side from the input terminal 12 becomes the value of a parallel resultant resistance {(RP . RN/(RP+RN)}, which consists of the diffusion resistances RN and RP and is lower than a serial resultant resistance (Rp+RN) for a conventional input protective circuit. A CR time constant determined by a parasitic capacity or the like in the C-MOS inverter and the value of the resultant resistance on the input side of the C-MOS inverter can be formed smaller than previously. Thus, a propagation delay time can be shortened to obtain a high speed. |