发明名称 OPTIMUM DETECTION SYSTEM FOR SYNCHRONIZING WORD
摘要 PURPOSE:To execute suitably the detection of a synchronizing word which comes to be a reference at the establishing process of synchronization and to quicken the pulling-in time of synchronization by selecting and setting the value of the optimum number of the allowable error in accordance with momentarily changing line quality. CONSTITUTION:A line quality measuring circuit 8 executes the the measurement of an element to determine the line quality of a transmission line and sends the measuring data to an allowable error number control circuit 2. The control circuit 2 counts the optimum number of the allowable error to inputted data, instructs the number of the allowable error specified corresponding to the data beforehand and sends the number of allowable errors control information to show the number of the allowable errors to a synchronizing word detecting circuit 1. The detecting circuit 1 is the same as the conventional technology, and when the number of bit error of an input signal exceeds the reference on the basis of the above-mentioned number of allowable errors, the synchronizing word is not detected and when the number of bit errors is within the reference, the synchronizing word is detected and the synchronizing word detecting signal is outputted.
申请公布号 JPS6333031(A) 申请公布日期 1988.02.12
申请号 JP19860176356 申请日期 1986.07.26
申请人 NEC CORP 发明人 SONEDAKA NORIYOSHI
分类号 H04L1/00;H04L1/20;H04L7/08 主分类号 H04L1/00
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