| 摘要 |
An improved driver circuit for an integrated gate circuit using Gallium Arsenide direct coupled FET logic. The push-pull driver circuit generally comprises an enhancement mode voltage follower transistor for driving a load during a first logic transition, and an enhancement mode pull-down transistor for driving this load during a second logic transition. Since only one of these transistors are conductive during these logic transitions (i.e., LO to HI, and HI to LO), little or no static current flows through these transistor means during steady state conditions. Thus, particularly for large capacitive loads, the driver circuit will be considerably faster than conventional DCFL technology, while not causing a significant increase in the power consumed by the push-pull driver circuit.
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