| 摘要 |
PURPOSE:To allow the titled circuit to cope with even high speed operation by designing the circuit so that only an output of a gate circuit corresponding to a reception data series and a synchronizing signal pattern both of the polarity of bits of which are dissident goes to a high level and an output level of an operational amplifier is increased as number of coincident bits increases and the frame synchronization detecting state is brought when the output level is larger than the threshold voltage so as to eliminate a timing control circuit. CONSTITUTION:Inputs E1-EN to a gate circuit 3 are the exclusive OR between N-bit reception data series RD1-RDN from the past till the present point of time outputted from a serial/parallel conversion shift register 1 and N-bit synchronizing pattern signals S1-SN, and the output to the coincident bits among outputs 01-0N of the gate circuit 3 is in the open state and only the output corresponding to dissident bits goes to an H level. When N-bit reception data series RD1-RDN have an error below the allowable bit number na-bit at the synchronization detection and are coincident with a reception frame synchronization pattern, an output DET of a level comparator 5 goes to an H level and the presence of reception frame synchronization is outputted externally. |
